1. Field of the Invention
The present invention relates to a delay circuit for delaying a signal by a predetermined period of time.
2. Description of the Related Art
FIG. 18 is a block diagram of a conventional delay circuit, FIG. 19 is a circuit diagram thereof, and FIG. 20 is a pattern plan view of the delay circuit formed as an integrated circuit.
As shown in FIGS. 8-20, a plurality of inverters 200 are connected in cascade between an input terminal IN and an output terminal OUT, and each of the inverters has a delay time which depends upon the on-resistance of transistors 202 and 204 and the capacitance added to an output signal of the inverter. Since, however, the conventional delay circuit includes the plural inverters 200, its pattern area is considerable, as shown in FIG. 20.
To reduce the size of the pattern area, the number of the inverters can be decreased by increasing the time constant of each of the inverters incorporated in the circuit, and lengthening the delay time thereof. A delay circuit having a decreased number of inverters is shown in FIG. 21, in which the gates of MOSFETs 202 and 204 constituting an inverter 200 are lengthened to increase the time constant of the inverter. However, lengthening the gates is not in itself a solution to reducing the pattern area. If the gates are lengthened too much, dispersion of parameters of semiconductor devices occurs.
When a mask shrink rate is changed in a delay circuit of MOS FETs each having a long gate length, the rate of variation in delay time does not conform to that of the other circuits. More specifically, if a mask is shrunk, the delay time is changed. For this reason, when the mask shrink rate is changed, the delay circuit has to be redesigned to ensure its proper operation, which increases the circuit development time.
FIGS. 22 and 23 show other conventional delay circuits. The delay circuit shown in FIG. 22 includes a capacitor C, while that shown in FIG. 23 includes a resistor R. Since the capacitor and resistor differ from other circuit elements, i.e., MOS FETs in their influence of dispersion of parameters of semiconductor devices, the delay time of signals deviates from a set value, or the delay circuits do not perform their operations perfectly.
As described above, the conventional delay circuits have to have a large pattern area in order to obtain the desired signal delay time, and thus the pattern area per delay time is enlarged. Further, they have drawbacks in that the parameters of semiconductor devices can easily vary in the process of manufacturing an integrated circuit, changing the delay time if the shrink rate of a mask for manufacturing the integrated circuit changes.